TABLE OF CONTENTS

Overview
Block Diagram
External Ports
Processor
   processing_system7_0
Busses
   axi4lite_0
Peripherals
   ADC_SPI
   BTNs_5Bits
   DAC_SPI
   LEDs_8Bits
   SWs_8Bits
   axi_timer_0
   axi_timer_1
   bluetooth_uart
   keypad
Timing Information
Overview TOC
Resources Used
1   Processing System
1   AXI Interconnect
2   AXI Timer/Counter
4   AXI General Purpose IO
1   AXI UART (Lite)
2   AXI SPI Interface
Specifics
Generated Wed Apr 02 16:44:24 2014
EDK Version 14.6
Device Family zynq
Device xc7z020clg484-1

Block Diagram TOC

BlockDiagram
External Ports TOC

These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
ADC_SPI ADC_SPI_MISO_pin IO 1 ADC_SPI_MISO
ADC_SPI ADC_SPI_MOSI_pin IO 1 ADC_SPI_MOSI
ADC_SPI ADC_SPI_SCK_pin IO 1 ADC_SPI_SCK
ADC_SPI ADC_SPI_SS_pin IO 1 ADC_SPI_SS
BTNs_5Bits BTNs_5Bits_TRI_IO IO 0:4 BTNs_5Bits_TRI_IO
DAC_SPI DAC_SPI_MISO_pin IO 1 DAC_SPI_MISO
DAC_SPI DAC_SPI_MOSI_pin IO 1 DAC_SPI_MOSI
DAC_SPI DAC_SPI_SCK_pin IO 1 DAC_SPI_SCK
DAC_SPI DAC_SPI_SS_pin IO 1 DAC_SPI_SS
LEDs_8Bits LEDs_8Bits_TRI_IO O 0:7 LEDs_8Bits_TRI_IO
SWs_8Bits SWs_8Bits_TRI_IO IO 0:7 SWs_8Bits_TRI_IO
bluetooth_uart bluetooth_uart_RX_pin I 1 bluetooth_uart_RX
bluetooth_uart bluetooth_uart_TX_pin O 1 bluetooth_uart_TX
keypad keypad_GPIO_IO_pin IO 0:7 keypad_GPIO_IO
processing_system7_0 processing_system7_0_PS_CLK I 1 processing_system7_0_PS_CLK  CLK 
processing_system7_0 processing_system7_0_PS_PORB I 1 processing_system7_0_PS_PORB
processing_system7_0 processing_system7_0_PS_SRSTB I 1 processing_system7_0_PS_SRSTB
processing_system7_0 processing_system7_0_DDR_Addr IO 0:14 processing_system7_0_DDR_Addr
processing_system7_0 processing_system7_0_DDR_BankAddr IO 0:2 processing_system7_0_DDR_BankAddr
processing_system7_0 processing_system7_0_DDR_CAS_n IO 1 processing_system7_0_DDR_CAS_n
processing_system7_0 processing_system7_0_DDR_CKE IO 1 processing_system7_0_DDR_CKE
processing_system7_0 processing_system7_0_DDR_CS_n IO 1 processing_system7_0_DDR_CS_n
processing_system7_0 processing_system7_0_DDR_Clk IO 1 processing_system7_0_DDR_Clk  CLK 
processing_system7_0 processing_system7_0_DDR_Clk_n IO 1 processing_system7_0_DDR_Clk_n  CLK 
processing_system7_0 processing_system7_0_DDR_DM IO 0:3 processing_system7_0_DDR_DM
processing_system7_0 processing_system7_0_DDR_DQ IO 0:31 processing_system7_0_DDR_DQ
processing_system7_0 processing_system7_0_DDR_DQS IO 0:3 processing_system7_0_DDR_DQS
processing_system7_0 processing_system7_0_DDR_DQS_n IO 0:3 processing_system7_0_DDR_DQS_n
processing_system7_0 processing_system7_0_DDR_DRSTB IO 1 processing_system7_0_DDR_DRSTB  RESET 
processing_system7_0 processing_system7_0_DDR_ODT IO 1 processing_system7_0_DDR_ODT
processing_system7_0 processing_system7_0_DDR_RAS_n IO 1 processing_system7_0_DDR_RAS_n
processing_system7_0 processing_system7_0_DDR_VRN IO 1 processing_system7_0_DDR_VRN
processing_system7_0 processing_system7_0_DDR_VRP IO 1 processing_system7_0_DDR_VRP
processing_system7_0 processing_system7_0_MIO IO 0:53 processing_system7_0_MIO
processing_system7_0 processing_system7_0_DDR_WEB_pin O 1 processing_system7_0_DDR_WEB


Processors TOC

processing_system7_0   Processing System
Processing System wrapper for Series 7

IP Specs
Core Version Documentation
processing_system7 4.03.a IP


processing_system7_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 MIO IO 1 processing_system7_0_MIO
1 PS_SRSTB I 1 processing_system7_0_PS_SRSTB
2 PS_CLK I 1 processing_system7_0_PS_CLK
3 PS_PORB I 1 processing_system7_0_PS_PORB
4 DDR_Clk IO 1 processing_system7_0_DDR_Clk
5 DDR_Clk_n IO 1 processing_system7_0_DDR_Clk_n
6 DDR_CKE IO 1 processing_system7_0_DDR_CKE
7 DDR_CS_n IO 1 processing_system7_0_DDR_CS_n
8 DDR_RAS_n IO 1 processing_system7_0_DDR_RAS_n
9 DDR_CAS_n IO 1 processing_system7_0_DDR_CAS_n
10 DDR_WEB O 1 processing_system7_0_DDR_WEB
11 DDR_BankAddr IO 1 processing_system7_0_DDR_BankAddr
12 DDR_Addr IO 1 processing_system7_0_DDR_Addr
13 DDR_ODT IO 1 processing_system7_0_DDR_ODT
14 DDR_DRSTB IO 1 processing_system7_0_DDR_DRSTB
15 DDR_DQ IO 1 processing_system7_0_DDR_DQ
16 DDR_DM IO 1 processing_system7_0_DDR_DM
17 DDR_DQS IO 1 processing_system7_0_DDR_DQS
18 DDR_DQS_n IO 1 processing_system7_0_DDR_DQS_n
19 DDR_VRN IO 1 processing_system7_0_DDR_VRN
20 DDR_VRP IO 1 processing_system7_0_DDR_VRP
21 FCLK_CLK0 O 1 processing_system7_0_FCLK_CLK0
22 FCLK_RESET0_N O 1 processing_system7_0_FCLK_RESET0_N_0
23 M_AXI_GP0_ACLK I 1 processing_system7_0_FCLK_CLK0
24 IRQ_F2P I 1 axi_timer_0_Interrupt & axi_timer_1_Interrupt & ADC_SPI_IP2INTC_Irpt & DAC_SPI_IP2INTC_Irpt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
M_AXI_GP0 MASTER AXI axi4lite_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_EN_EMIO_CAN0 0
C_EN_EMIO_CAN1 0
C_EN_EMIO_ENET0 0
C_EN_EMIO_ENET1 0
C_EN_EMIO_GPIO 0
C_EN_EMIO_I2C0 0
C_EN_EMIO_I2C1 0
C_EN_EMIO_PJTAG 0
C_EN_EMIO_SDIO0 0
C_EN_EMIO_CD_SDIO0 0
C_EN_EMIO_WP_SDIO0 0
C_EN_EMIO_SDIO1 0
C_EN_EMIO_CD_SDIO1 0
C_EN_EMIO_WP_SDIO1 0
C_EN_EMIO_SPI0 0
C_EN_EMIO_SPI1 0
C_EN_EMIO_UART0 0
C_EN_EMIO_UART1 0
C_EN_EMIO_MODEM_UART0 0
C_EN_EMIO_MODEM_UART1 0
C_EN_EMIO_TTC0 1
C_EN_EMIO_TTC1 0
C_EN_EMIO_WDT 0
C_EN_EMIO_TRACE 0
C_USE_M_AXI_GP0 1
C_USE_M_AXI_GP1 0
C_USE_S_AXI_GP0 0
C_USE_S_AXI_GP1 0
C_USE_S_AXI_ACP 0
C_USE_S_AXI_HP0 0
C_USE_S_AXI_HP1 0
C_USE_S_AXI_HP2 0
C_USE_S_AXI_HP3 0
C_S_AXI_GP0_ENABLE_LOWOCM_DDR 0
C_S_AXI_GP1_ENABLE_LOWOCM_DDR 0
C_S_AXI_ACP_ENABLE_HIGHOCM 0
C_S_AXI_HP0_ENABLE_HIGHOCM 0
C_S_AXI_HP1_ENABLE_HIGHOCM 0
C_S_AXI_HP2_ENABLE_HIGHOCM 0
C_S_AXI_HP3_ENABLE_HIGHOCM 0
C_USE_DMA0 0
C_USE_DMA1 0
C_USE_DMA2 0
C_USE_DMA3 0
C_USE_TRACE 0
C_INCLUDE_TRACE_BUFFER 0
C_TRACE_BUFFER_FIFO_SIZE 128
USE_TRACE_DATA_EDGE_DETECTOR 0
C_TRACE_BUFFER_CLOCK_DELAY 12
C_USE_CROSS_TRIGGER 0
C_USE_CR_FABRIC 1
C_USE_AXI_FABRIC_IDLE 0
C_USE_DDR_BYPASS 0
C_USE_FABRIC_INTERRUPT 1
C_USE_PROC_EVENT_BUS 0
C_EN_EMIO_SRAM_INT 0
C_EMIO_GPIO_WIDTH 64
C_INCLUDE_ACP_TRANS_CHECK 0
C_USE_DEFAULT_ACP_USER_VAL 0
C_S_AXI_ACP_ARUSER_VAL 31
C_S_AXI_ACP_AWUSER_VAL 31
C_DQ_WIDTH 32
C_DQS_WIDTH 4
C_DM_WIDTH 4
C_MIO_PRIMITIVE 54
C_PACKAGE_NAME clg484
C_PS7_SI_REV PRODUCTION
C_UART_BAUD_RATE 115200
C_DDR_RAM_BASEADDR 0x00000000
C_DDR_RAM_HIGHADDR 0x1FFFFFFF
C_UART0_BASEADDR 0xE0000000
C_UART0_HIGHADDR 0xE0000FFF
C_UART1_BASEADDR 0xE0001000
C_UART1_HIGHADDR 0xE0001FFF
C_I2C0_BASEADDR 0xE0004000
C_I2C0_HIGHADDR 0xE0004FFF
C_I2C1_BASEADDR 0xE0005000
C_I2C1_HIGHADDR 0xE0005FFF
C_SPI0_BASEADDR 0xE0006000
C_SPI0_HIGHADDR 0xE0006FFF
C_SPI1_BASEADDR 0xE0007000
C_SPI1_HIGHADDR 0xE0007FFF
C_CAN0_BASEADDR 0xE0008000
C_CAN0_HIGHADDR 0xE0008FFF
C_CAN1_BASEADDR 0xE0009000
C_CAN1_HIGHADDR 0xE0009FFF
C_GPIO_BASEADDR 0xE000A000
C_GPIO_HIGHADDR 0xE000AFFF
C_ENET0_BASEADDR 0xE000B000
C_ENET0_HIGHADDR 0xE000BFFF
C_ENET1_BASEADDR 0xE000C000
C_ENET1_HIGHADDR 0xE000CFFF
C_SDIO0_BASEADDR 0xE0100000
C_SDIO0_HIGHADDR 0xE0100FFF
C_SDIO1_BASEADDR 0xE0101000
C_SDIO1_HIGHADDR 0xE0101FFF
C_USB0_BASEADDR 0xE0002000
C_USB0_HIGHADDR 0xE0002FFF
C_USB1_BASEADDR 0xE0003000
C_USB1_HIGHADDR 0xE0003FFF
C_TTC0_BASEADDR 0xF8001000
C_TTC0_HIGHADDR 0xF8001FFF
C_TTC1_BASEADDR 0xF8002000
C_TTC1_HIGHADDR 0xF8002FFF
C_M_AXI_GP0_PROTOCOL AXI3
C_M_AXI_GP0_ID_WIDTH 12
C_M_AXI_GP0_ADDR_WIDTH 32
C_M_AXI_GP0_DATA_WIDTH 32
C_M_AXI_GP0_ENABLE_STATIC_REMAP 0
C_M_AXI_GP0_SUPPORTS_NARROW_BURST 0
C_M_AXI_GP0_SUPPORTS_REORDERING 0
C_INTERCONNECT_M_AXI_GP0_WRITE_ISSUING 8
C_INTERCONNECT_M_AXI_GP0_READ_ISSUING 8
C_M_AXI_GP1_PROTOCOL AXI3
C_M_AXI_GP1_ID_WIDTH 12
C_M_AXI_GP1_ADDR_WIDTH 32
C_M_AXI_GP1_DATA_WIDTH 32
 
Name Value
C_M_AXI_GP1_ENABLE_STATIC_REMAP 0
C_M_AXI_GP1_SUPPORTS_NARROW_BURST 0
C_M_AXI_GP1_SUPPORTS_REORDERING 0
C_INTERCONNECT_M_AXI_GP1_WRITE_ISSUING 8
C_INTERCONNECT_M_AXI_GP1_READ_ISSUING 8
C_S_AXI_GP0_PROTOCOL AXI3
C_S_AXI_GP0_ID_WIDTH 6
C_S_AXI_GP0_ADDR_WIDTH 32
C_S_AXI_GP0_DATA_WIDTH 32
C_INTERCONNECT_S_AXI_GP0_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_GP0_READ_ACCEPTANCE 8
C_S_AXI_GP1_PROTOCOL AXI3
C_S_AXI_GP1_ID_WIDTH 6
C_S_AXI_GP1_ADDR_WIDTH 32
C_S_AXI_GP1_DATA_WIDTH 32
C_INTERCONNECT_S_AXI_GP1_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_GP1_READ_ACCEPTANCE 8
C_S_AXI_ACP_PROTOCOL AXI3
C_S_AXI_ACP_ID_WIDTH 3
C_S_AXI_ACP_ADDR_WIDTH 32
C_S_AXI_ACP_DATA_WIDTH 64
C_S_AXI_ACP_SUPPORTS_USER_SIGNALS 1
C_S_AXI_ACP_ARUSER_WIDTH 5
C_S_AXI_ACP_AWUSER_WIDTH 5
C_INTERCONNECT_S_AXI_ACP_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_ACP_READ_ACCEPTANCE 8
C_S_AXI_HP0_PROTOCOL AXI3
C_S_AXI_HP0_ID_WIDTH 6
C_S_AXI_HP0_ADDR_WIDTH 32
C_S_AXI_HP0_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP0_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP0_READ_ACCEPTANCE 8
C_S_AXI_HP1_PROTOCOL AXI3
C_S_AXI_HP1_ID_WIDTH 6
C_S_AXI_HP1_ADDR_WIDTH 32
C_S_AXI_HP1_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP1_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP1_READ_ACCEPTANCE 8
C_S_AXI_HP2_PROTOCOL AXI3
C_S_AXI_HP2_ID_WIDTH 6
C_S_AXI_HP2_ADDR_WIDTH 32
C_S_AXI_HP2_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP2_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP2_READ_ACCEPTANCE 8
C_S_AXI_HP3_PROTOCOL AXI3
C_S_AXI_HP3_ID_WIDTH 6
C_S_AXI_HP3_ADDR_WIDTH 32
C_S_AXI_HP3_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP3_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP3_READ_ACCEPTANCE 8
C_S_AXI_GP0_BASEADDR 0xE0000000
C_S_AXI_GP0_HIGHADDR 0xFFFFFFFF
C_S_AXI_GP0_LOWOCM_DDR_BASEADDR 0x00000000
C_S_AXI_GP0_LOWOCM_DDR_HIGHADDR 0x3FFFFFFF
C_S_AXI_GP1_BASEADDR 0xE0000000
C_S_AXI_GP1_HIGHADDR 0xFFFFFFFF
C_S_AXI_GP1_LOWOCM_DDR_BASEADDR 0x00000000
C_S_AXI_GP1_LOWOCM_DDR_HIGHADDR 0x3FFFFFFF
C_S_AXI_ACP_BASEADDR 0x00000000
C_S_AXI_ACP_HIGHADDR 0x3FFFFFFF
C_S_AXI_ACP_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_ACP_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP0_BASEADDR 0x00000000
C_S_AXI_HP0_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP0_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP0_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP1_BASEADDR 0x00000000
C_S_AXI_HP1_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP1_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP1_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP2_BASEADDR 0x00000000
C_S_AXI_HP2_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP2_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP2_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP3_BASEADDR 0x00000000
C_S_AXI_HP3_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP3_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP3_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_M_AXI_GP0_SUPPORTS_THREADS 1
C_M_AXI_GP0_THREAD_ID_WIDTH 12
C_M_AXI_GP1_SUPPORTS_THREADS 1
C_M_AXI_GP1_THREAD_ID_WIDTH 12
C_NUM_F2P_INTR_INPUTS 2
C_EN_DDR 1
C_EN_SMC 0
C_EN_QSPI 1
C_EN_CAN0 0
C_EN_CAN1 0
C_EN_ENET0 1
C_EN_ENET1 0
C_EN_GPIO 1
C_EN_I2C0 0
C_EN_I2C1 0
C_EN_PJTAG 0
C_EN_SDIO0 1
C_EN_SDIO1 0
C_EN_SPI0 0
C_EN_SPI1 0
C_EN_UART0 0
C_EN_UART1 1
C_EN_MODEM_UART0 0
C_EN_MODEM_UART1 0
C_EN_TTC0 1
C_EN_TTC1 0
C_EN_WDT 0
C_EN_TRACE 0
C_EN_USB0 1
C_EN_USB1 0
C_EN_4K_TIMER 0
C_FCLK_CLK0_FREQ 100000000
C_FCLK_CLK1_FREQ 142857132
C_FCLK_CLK2_FREQ 50000000
C_FCLK_CLK3_FREQ 50000000
C_FCLK_CLK0_BUF TRUE
C_FCLK_CLK1_BUF TRUE
C_FCLK_CLK2_BUF TRUE
C_FCLK_CLK3_BUF TRUE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Busses TOC

axi4lite_0   AXI Interconnect
AXI4 Memory-Mapped Interconnect

IP Specs
Core Version Documentation
axi_interconnect 1.06.a IP


axi4lite_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 interconnect_aclk I 1 processing_system7_0_FCLK_CLK0
1 INTERCONNECT_ARESETN I 1 processing_system7_0_FCLK_RESET0_N_0
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
processing_system7_0 MASTER M_AXI_GP0
axi_timer_1 SLAVE S_AXI
axi_timer_0 SLAVE S_AXI
SWs_8Bits SLAVE S_AXI
LEDs_8Bits SLAVE S_AXI
BTNs_5Bits SLAVE S_AXI
bluetooth_uart SLAVE S_AXI
ADC_SPI SLAVE S_AXI
DAC_SPI SLAVE S_AXI
keypad SLAVE S_AXI


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY rtl
C_BASEFAMILY rtl
C_NUM_SLAVE_SLOTS 1
C_NUM_MASTER_SLOTS 1
C_AXI_ID_WIDTH 1
C_AXI_ADDR_WIDTH 32
C_AXI_DATA_MAX_WIDTH 32
C_S_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH 32
C_S_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT 0b0000000000000000
C_S_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_M_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO 1
C_S_AXI_SUPPORTS_WRITE 0b1111111111111111
C_S_AXI_SUPPORTS_READ 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE 0b1111111111111111
C_M_AXI_SUPPORTS_READ 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS 0
C_AXI_AWUSER_WIDTH 1
C_AXI_ARUSER_WIDTH 1
C_AXI_WUSER_WIDTH 1
C_AXI_RUSER_WIDTH 1
C_AXI_BUSER_WIDTH 1
C_AXI_CONNECTIVITY 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
Name Value
C_M_AXI_READ_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY 0b0000000000000000
C_S_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER 0
C_INTERCONNECT_CONNECTIVITY_MODE 0
C_USE_CTRL_PORT 0
C_USE_INTERRUPT 1
C_RANGE_CHECK 2
C_S_AXI_CTRL_PROTOCOL AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_BASEADDR 0xFFFFFFFF
C_HIGHADDR 0x00000000
C_DEBUG 0
C_S_AXI_DEBUG_SLOT 0
C_M_AXI_DEBUG_SLOT 0
C_MAX_DEBUG_THREADS 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Peripherals TOC

ADC_SPI   AXI SPI Interface
AXI to Motorola Serial Peripheral Interface (SPI) adapter

IP Specs
Core Version Documentation
axi_spi 1.02.a IP


ADC_SPI IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 SCK IO 1 ADC_SPI_SCK
2 MISO IO 1 ADC_SPI_MISO
3 MOSI IO 1 ADC_SPI_MOSI
4 SS IO 1 ADC_SPI_SS
5 IP2INTC_Irpt O 1 ADC_SPI_IP2INTC_Irpt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x42000000
C_HIGHADDR 0x4200FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_FIFO_EXIST 1
 
Name Value
C_SCK_RATIO 32
C_NUM_SS_BITS 1
C_NUM_TRANSFER_BITS 16
C_S_AXI_PROTOCOL AXI4LITE
C_INSTANCE axi_spi_inst
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


BTNs_5Bits   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


BTNs_5Bits IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 GPIO_IO IO 1 BTNs_5Bits_TRI_IO
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_gpio_inst
C_BASEADDR 0x41240000
C_HIGHADDR 0x4124FFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 5
C_GPIO2_WIDTH 32
C_ALL_INPUTS 1
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


DAC_SPI   AXI SPI Interface
AXI to Motorola Serial Peripheral Interface (SPI) adapter

IP Specs
Core Version Documentation
axi_spi 1.02.a IP


DAC_SPI IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 SCK IO 1 DAC_SPI_SCK
2 MISO IO 1 DAC_SPI_MISO
3 MOSI IO 1 DAC_SPI_MOSI
4 SS IO 1 DAC_SPI_SS
5 IP2INTC_Irpt O 1 DAC_SPI_IP2INTC_Irpt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x42040000
C_HIGHADDR 0x4204FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_FIFO_EXIST 1
 
Name Value
C_SCK_RATIO 32
C_NUM_SS_BITS 1
C_NUM_TRANSFER_BITS 16
C_S_AXI_PROTOCOL AXI4LITE
C_INSTANCE axi_spi_inst
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


LEDs_8Bits   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


LEDs_8Bits IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 GPIO_IO_O O 1 LEDs_8Bits_TRI_IO
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_gpio_inst
C_BASEADDR 0x41220000
C_HIGHADDR 0x4122FFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


SWs_8Bits   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


SWs_8Bits IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 GPIO_IO IO 1 SWs_8Bits_TRI_IO
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_gpio_inst
C_BASEADDR 0x41200000
C_HIGHADDR 0x4120FFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 1
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_timer_0   AXI Timer/Counter
Timer counter with AXI interface

IP Specs
Core Version Documentation
axi_timer 1.03.a IP


axi_timer_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 Interrupt O 1 axi_timer_0_Interrupt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_PROTOCOL AXI4LITE
C_FAMILY virtex6
C_INSTANCE axi_timer_inst
C_COUNT_WIDTH 32
C_ONE_TIMER_ONLY 0
C_TRIG0_ASSERT 1
C_TRIG1_ASSERT 1
 
Name Value
C_GEN0_ASSERT 1
C_GEN1_ASSERT 1
C_BASEADDR 0x42820000
C_HIGHADDR 0x4282FFFF
C_S_AXI_ADDR_WIDTH 5
C_S_AXI_DATA_WIDTH 32
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_timer_1   AXI Timer/Counter
Timer counter with AXI interface

IP Specs
Core Version Documentation
axi_timer 1.03.a IP


axi_timer_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 Interrupt O 1 axi_timer_1_Interrupt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_PROTOCOL AXI4LITE
C_FAMILY virtex6
C_INSTANCE axi_timer_inst
C_COUNT_WIDTH 32
C_ONE_TIMER_ONLY 0
C_TRIG0_ASSERT 1
C_TRIG1_ASSERT 1
 
Name Value
C_GEN0_ASSERT 1
C_GEN1_ASSERT 1
C_BASEADDR 0x42800000
C_HIGHADDR 0x4280FFFF
C_S_AXI_ADDR_WIDTH 5
C_S_AXI_DATA_WIDTH 32
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


bluetooth_uart   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

IP Specs
Core Version Documentation
axi_uartlite 1.02.a IP


bluetooth_uart IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 RX I 1 bluetooth_uart_RX
2 TX O 1 bluetooth_uart_TX
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_uartlite_inst
C_S_AXI_ACLK_FREQ_HZ 100000000
C_BASEADDR 0x42C00000
C_HIGHADDR 0x42C0FFFF
C_S_AXI_ADDR_WIDTH 4
 
Name Value
C_S_AXI_DATA_WIDTH 32
C_BAUDRATE 115200
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


keypad   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


keypad IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 GPIO_IO IO 1 keypad_GPIO_IO
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_gpio_inst
C_BASEADDR 0x41280000
C_HIGHADDR 0x4128FFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 1
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Timing Information TOC


Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.