This is basic block diagram of the system.

The basic process is the following:

1. Read numbers from the receiver board using the ADC at a rate of FS=100 kHz
2. Low pass filter the samples (using an FIR filter)
3. Down sample the data to a rate of FS=10 kHz
4. Filter the data through the 10 bandpass filters (using 10 IIR filters)
5. Compute a running power

To better understand this process let's look

Low pass filtering We are going to start by looking at a very short time scale in order to easily see what things look like a t